Computer memories may be conveniently classified in terms of whether or not the memory retains the information stored therein when power is removed from the memory. Conventional DRAMs and SRAMs are examples of memories that lose their contents when power is removed. EEPROM and flash RAM are examples of non-volatile memories. The cost of non-volatile memories per bit remains sufficiently high to discourage their use in many applications. In addition, the underlying memory structures may only be written a relatively small number of times compared to volatile memories. For example, an EEPROM memory cell can only be written approximately 10.sup.4 times. In addition, the time required to write data into an EEPROM is much longer than that required to write volatile memories. Hence, EEPROM cells have a relatively limited class of applications.
One class of non-volatile memory device stores information by altering the direction of polarization of a ferroelectric dielectric layer within the device. These devices are structurally similar to capacitors in which the dielectric layer is replaced by a ferroelectric material. In fact, one class of devices is structurally a capacitor in which the dielectric layer is replaced by a ferroelectric layer. In these devices, the ferroelectric dielectric may be polarized in one of two directions. The direction of polarization is used to store information, a "1" corresponding to one direction of polarization and a "0" corresponding to the other direction of polarization. The polarization of the dielectric is maintained when power is removed from the system, thus providing non-volatile operation.
The direction of the polarization may be sensed by applying a potential sufficient to switch the polarization across the capacitor. For the purposes of this discussion, assume that the applied potential difference is such that it would switch the dielectric to the polarization state corresponding to a "1" . If the capacitor was polarized such that it stored a "1" prior to the application of the read potential, the polarization will not be altered by the read voltage. However, if the capacitor was polarized such that it stored a "0" prior to the application of the read potential, the polarization direction will switch. This switching will give rise to a current that flows from one plate of the capacitor to the other. A sense amplifier measures the current that flows in response to the read potential to determine the state of the capacitor. Once the capacitor has been read, the data must be rewritten in the capacitor if the read potential caused the state of the capacitor to switch.
A ferroelectric capacitor is normally constructed by depositing a layer of the ferroelectric material on a bottom electrode and then depositing a top electrode on the ferroelectric layer. Ferroelectric layers based on PZT are well known to those skilled in the art. These materials are heated to relatively high temperatures after deposition to provide a perovskite structure having the desired ferroelectric properties. After the annealing process, the dielectric film contains a large number of domains. Each individual domain has a spontaneous polarization equivalent to that of a mono-domain single crystal of the perovskite material. At the end of the deposition process, domains are usually randomly oriented.
While this type of memory has been known to the art for some time, commercial realizations of this type of memory have been limited because of two problems, commonly referred to as "imprint" and "fatigue" . Imprint is the tendency of a ferroelectric capacitor to exhibit a shift of its hysteresis curve along the voltage axis in either the positive or negative direction depending on the data stored therein. This tendency can lead to a logic state failure for either of two reasons. First, after a sufficient shift, both logic states appear the same to a sense amplifier. Second, the coercive voltage becomes too large to be switched by the available programming voltage. When either case is encountered, a memory cell based on the capacitor becomes useless.
Fatigue is the decrease in the magnitude of the remnant polarization of the dielectric layer with the number of times the direction of polarization is changed. Since the amount of charge displaced when the capacitor is switched is related to the remnant polarization, the capacitor finally reaches a point at which there is insufficient charge displaced to detect. At this point, a memory cell based on the capacitor also becomes useless.
Memory devices based on ferroelectric FETs are also known to the art. These structures may be viewed as a capacitor in which the top electrode has been replaced by a layer of semiconductor material having two electrodes deposited thereon and spaced apart from each other. Data is once again stored in the direction of polarization of the ferroelectric dielectric layer. The state of polarization gives rise to an electric field which alters the resistivity of the semiconductor layer. That is, the resistance measured between the two electrodes depends on the direction of polarization of the ferroelectric layer. This class of devices has the advantage of not requiring the ferroelectric layer to be switched each time the device is read.
Memories based on prior art ferroelectric FETs exhibit retention problems that limit the usefulness of such devices. If data is not periodically rewritten, the data is lost. Prior art ferroelectric FET memories also exhibit fatigue problems.
To simplify the following discussion, the term ferroelectric memory cell will be defined to include both ferroelectric FETs and ferroelectric capacitors. As noted above, these devices may be viewed as differing in the manner in which the top electrode of a capacitor is constructed.
While more or less ideal ferroelectric memory cells can be demonstrated in the laboratory, attempts to incorporate these cells into packaged memory chips have failed to provide satisfactory parts. In general, a memory chip includes circuitry constructed on a silicon substrate utilizing conventional CMOS fabrication techniques. The CMOS circuitry provides the isolation transistors, sense amplifiers, and decoding circuitry needed to pick specific ferroelectric memory cells for reading and writing. The ferroelectric memory cells are typically constructed after the CMOS circuitry has been constructed on pads adjacent to the CMOS isolation transistors. However, memories in which the ferroelectric memory cells are constructed over the CMOS isolation transistors have also been described. In the latter case, an isolation layer such as silicon dioxide is first deposited over the CMOS structures.
After the ferroelectric memory cells have been constructed over the CMOS circuitry, a number of further processing steps are needed to complete the memory. Two of these are common to all types of memories. First, various connections between the ferroelectric memory cells and the underlying CMOS circuitry must be made by depositing a conductor such as aluminum. This involves depositing a dielectric layer over the circuit on which the metal is deposited. The preferred dielectric in conventional CMOS circuits is silicon nitride; however, the deposition conditions for silicon nitride damage the underlying ferroelectric layers. Accordingly, silicon dioxide is normally used. However, even the silicon dioxide causes damage to the ferroelectric materials. Hence, prior art ferroelectric memories are limited to one metal interconnect layer, since the accumulated damage resulting from the deposition of multiple layers is unacceptable.
Second, the entire circuit is then covered with a passivation layer such as silicon dioxide. The passivated wafer is then subjected to a forming gas anneal in which it is heated to 350.degree. to 400.degree. C. in a hydrogen/nitrogen atmosphere.
While satisfactory devices can be demonstrated up to the completion of these last two steps, something in these steps leads to deterioration in device performance. After the forming gas anneal, capacitor based devices exhibit unacceptable imprint problems and poor hysteresis curves. Similarly, ferroelectric FET based devices exhibit poor hysteresis curves and poor data retention.
Broadly, it is the object of the present invention to provide an improved ferroelectric memory cell.
It is a further object of the present invention to provide a ferroelectric memory cell that still operates satisfactorily after being subjected to subsequent processing steps including a forming gas anneal.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.